System and method for memory element characterization

ABSTRACT

A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.

RELATED APPLICATION INFORMATION

This application is a Divisional application of allowed U.S. patentapplication Ser. No. 11/142,709 filed on Jun. 1, 2005, pending.

BACKGROUND

1. Technical Field

The present invention relates to circuit design and more particularly toa system and method for memory element characterization in latch-typecircuits.

2. Description of the Related Art

Latch-type circuits are employed in many electronic applications. Thedesign of a latch circuit is an important aspect of the circuit'sperformance. The characterization of latch-type circuits is particularlytedious, however.

Latch characterization is typically based on circuit simulationexperiments, mainly using transient analysis. In contrast to othercharacterization targets for library elements, e.g., propagation delay,there are no simulation experiments that can directly determine theset-up or hold-time of a latch.

Instead, a sequence of simulations with varying time delays betweenclock and data transition events are typically performed, essentially,in a search procedure for the situation when the settling time of theinternal latch starts degrading. As a consequence, the characterizationof the latch library elements becomes a very costly anddisproportionately large portion of the total characterization effort.

SUMMARY

A system and method for analyzing a memory element includes modeling thememory element using a simulation method and determining componentresponse characteristics for components of the memory element. Safetyregions are computed in a state space of the memory element, whichindicate stable states. A transient analysis is performed to determine apath and time needed to reach one of the safety regions. Based on thepath and time needed to reach one of the safety regions, a clockwaveform or waveforms are determined which place a corresponding statein that safety region.

A latch design system includes a modeling module configured to model alatch using a simulation method. A simulation module is configured todetermine component response characteristics for components of the latchand compute safety regions in a state space of the latch. The safetyregions indicate stable states for the latch. A transient analysismodule is configured to determine transient responses for the latch inan open state to geometrically determine a path and time needed to reachone of the safety regions. The path and the time are employed todetermine a clock waveform for placing a corresponding state in the oneof the safety regions.

These and other objects, features and advantages will become apparentfrom the following detailed description of illustrative embodimentsthereof, which is to be read in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 is a block/flow diagram showing an illustrative system/method foravoiding metastable states by determining characteristics includingset-up and hold times for a latch or memory circuit in accordance withone exemplary embodiment;

FIG. 2 is a schematic diagram of a latch circuit and response plots forgiven components on which an analysis is performed in accordance with anembodiment of the present invention;

FIG. 3 is a timing diagram of the latch circuit of FIG. 2 showing dataand clock signals for an open state for latching data in the latch inaccordance with an embodiment of the present invention;

FIG. 4 is a schematic diagram of the latch circuit of FIG. 2 showing theopen state;

FIG. 5 is a schematic diagram of the latch circuit of FIG. 2 showing aclosed state;

FIG. 6 is a plot of the states in the closed latch state;

FIG. 7 is a timing diagram of the latch circuit of FIG. 2 showing dataand clock signals and parameters associated with the signals, as welland plots showing the path taken and the time needed to reach a safetyregion in accordance with an embodiment of the present invention; and

FIG. 8 is diagram showing a state space for the open state of the latchof FIG. 2, and showing safety regions within the state space inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFFERED EMBODIMENTS

Embodiments of the present invention are directed to characterization ofmemory elements, such as latches. In a particularly useful embodiment, alatch design tool is provided, which may be implemented in software, andhas the ability to characterize circuits, e.g., latches.

Library characterizations could benefit from a geometric, dynamicalsystem-based approach in the following way. A geometric description ofregions in state space together with relevant time constants can bederived off-line by a few simulation experiments. Once this descriptionin constructed and stored, the response to numerous excitation patterns,e.g., signals with various slopes and relative delays between clock anddata signals can be evaluated with little additional computation effort.For example, an area can be defined in the state space, such that everytime an excitation trajectory passes through it, the set up or holdconstraints are violated. This information is collected and employed incharacterization of the simulated or actual circuit.

Embodiments of the present invention can take the form of an entirelyhardware embodiment, an entirely software embodiment or an embodimentincluding both hardware and software elements. In a preferredembodiment, the present invention is implemented in software, whichincludes but is not limited to firmware, resident software, microcode,etc.

Furthermore, the present invention can take the form of a computerprogram product accessible from a computer-usable or computer-readablemedium providing program code for use by or in connection with acomputer or any instruction execution system. For the purposes of thisdescription, a computer-usable or computer readable medium can be anyapparatus that may include, store, communicate, propagate, or transportthe program for use by or in connection with the instruction executionsystem, apparatus, or device. The medium can be an electronic, magnetic,optical, electromagnetic, infrared, or semiconductor system (orapparatus or device) or a propagation medium, Examples of acomputer-readable medium include a semiconductor or solid state memory,magnetic tape, a removable computer diskette, a random access memory(RAM), a read-only memory (ROM), a rigid magnetic disk and an opticaldisk. Current examples of optical disks include compact disk—read onlymemory (CD-ROM), compact disk—read/write (CD-R/W) and DVD.

A data processing system suitable for storing and/or executing programcode may include at least one processor coupled directly or indirectlyto memory elements through a system bus. The memory elements can includelocal memory employed during actual execution of the program code, bulkstorage, and cache memories which provide temporary storage of at leastsome program code to reduce the number of times code is retrieved frombulk storage during execution. Input/output or I/O devices (includingbut not limited to keyboards, displays, pointing devices, etc.) may becoupled to the system either directly or through intervening I/Ocontrollers.

Network adapters may also be coupled to the system to enable the dataprocessing system to become coupled to other data processing systems orremote printers or storage devices through intervening private or publicnetworks. Modems, cable modem and Ethernet cards are just a few of thecurrently available types of network adapters.

Circuits tested or simulated as described herein may be part of thedesign for an integrated circuit chip. The chip design may be created ina graphical computer programming language, and stored in a computerstorage medium (such as a disk, tape, physical hard drive, or virtualhard drive such as in a storage access network). If the designer doesnot fabricate chips or the photolithographic masks used to fabricatechips, the designer transmits the resulting design by physical means(e.g., by providing a copy of the storage medium storing the design) orelectronically (e.g., through the Internet) to such entities, directlyor indirectly. The stored design is then converted into the appropriateformat (e.g., GDSII) for the fabrication of photolithographic masks,which typically include multiple copies of the chip design in questionthat are to be formed on a wafer. The photolithographic masks areutilized to define areas of the wafer (and/or the layers thereon) to beetched or otherwise processed. The methods and tools as described hereinmay be employed in the fabrication of integrated circuit chips.

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, a block/flow diagram isshown for an illustrative embodiment of the present invention. Themethod/system depicted in FIG. 1 may be employed as a design system/toolfor designing memory elements, such as latches. One advantage of such assystem includes the ability to pre-calculate characteristics todetermine points of interest in a characteristic plot or state map. Inthis way, a simply lookup table may be used to apply the response tolater conditions to achieve a rapid result without having to re-simulatethe entire circuit. This is particularly useful with set and hold timecomputations for latches.

In block 10, a memory element candidate is selected or designed. Amemory element may include a latch. A latch is an electrical elementthat includes two or more stable states and may be switched between tostore information. The latch may include a metastable state between thestable states. This metastable region is preferably avoided.

In block 12, a model of the circuit or the memory element is provided.This may include an analytical model, e.g., equations, a software model,e.g., a SPICE™ model or the like, or any other simulation model that cansimulate the operation and response of the memory elements being tested.For the present example, the model includes equations for the circuitdepicted in FIG. 2. In a computer implemented embodiment, block 12 mayrepresent a modeling module.

In block 14, memory element pre-characterization is performed. This maytake the form of simulation experiments. This may include performing, a“DC sweep” of operating points to determine a shape of the componentcharacteristics. A static (vector-less) analysis of the latch circuitsdetermines the boundaries of regions of interest in state-space. Theseboundaries may include parameters such as response voltages, currents orother electrical characteristics for the elements or components in thecircuit to be analyzed. In the present example, circuit 100 of FIG. 2includes elements such as a pass gate 104 and inverters 105 which areanalyzed. FIG. 2 depicts a function g(x) for pass gate 104 and afunction f(x) for inverters 105, which define regions/points of interestfor these components. These points of interest may be stored as tablesand/or functional constraints.

In block 16, based upon the simulation experiments in block 14, safetyregions are computed. Safety regions in this example are depicted asrectangular shaped regions 120 and 122 in FIG. 8. While depicted asrectangles, safety regions 120 and 122 may take on many shapes andsizes, or may be adjusted to permit different analysis or test scenariosin the design of circuit 100 (FIG. 2). There may be one or more safetyregions in the system state space depending on the number of stablestates for the circuit.

Safety regions are regions of stability. Each safety region represents astate where the value of the data to be stored in the memory element orlatch is invariant.

In block 18, simulation experiments are performed on the memory element(e.g., latch 106) in its “open” state. The open state is where data isbeing latched into the memory element. The open state simulationincludes a transient analysis of the latch to determine the evolution ofthe state space and the time needed to reach the safety region. In otherwords, the time and path needed to reach an invariant or stable state.

For example, excitation of data {tilde over (d)}(τ) and clock {tildeover (c)}(τ) waveforms determine a trajectory in the state space. Thetrajectory is checked against the stored geometry of the safety regionto determine if it traverses the safety region. The path (evolution) andtime is stored. This analysis can be performed more efficiently (byorders of magnitude) over conventional circuit simulation techniques.

In block 20, set-up and hold time extraction is performed. Based on thestate-space evolution determined in block 18, without the simulationlimits of clock waveforms corresponding to the safety regions, clockwaveforms are determined which avoid metastability of the latch. This ispreferably performed using a geometric layout of the system space eitheron paper or in digital space.

The set-up and hold times can be obtained by performing this simplifiedgeometric analysis rather than time consuming conventional circuitsimulation. This may preferably include employing look-up tables todetermine safety regions and whether a given set of conditions fallswithin the safety regions.

Alternatively, the geometric analysis may become sufficiently efficientto be used in timing analysis, thus replacing set up and holdconstraints simulations.

In a system, which may be implemented by computer, blocks 14, 16, 18 and20 may be implemented together in a single module or independently in aplurality of different modules. For example, blocks 14 and 16 may be apart of a simulation module to obtain simulated results of the latch,while a transient analysis module may be embodied by blocks 18 and 20.Other combinations of functions are also contemplated.

The present invention will now be described in further detail in termsof an illustrative example using latch 106.

Referring to FIG. 2, the exemplary circuit 100 upon which the presentinvention is illustratively described is shown. Circuit 100 includes adata source {tilde over (d)}(τ) and a clock {tilde over (c)}(τ). Clock{tilde over (c)}(τ) is introduced to a passgate 104 having a transitionresponse given by g( ) . Latch element 106 includes capacitors C,inverters 105 and resistances R. ν₁, ν₂, ν₃, and ν₄ indicate the stateor electrical characteristic of the respective locations in the circuit100. Note that the numbered states ν₁, ν₂, ν₃, and ν₄ are not the sameas the parameter, ν, which will be described hereinafter.

The pass gate 104 acts as a switch to activate/deactivate he latch 106to change latch states or maintain the latch state during a hold period.Since the switch 104 provides a gradual response (g(x)) between states(e.g., “0” and “1”) and inverters 105 provide a gradual response (f(x))between states, metastable possibilities exist for the latch states.

In an ideal situation, switching between states is instantaneous (forboth the passgate 104 and the inverters 105). Ideally, function g( ) andf( ) would be steps functions having plateaus at each state. This is notthe case in real applications however, as seen by the response curvesfor g(x) and f(x). Let ν be a value, which indicates a point where anideal instantaneous switching of states should occur. That is, when x=ν,the step function switches between values. This point of interest may beapplied to the f(x) curve as a point of interest.

Referring to FIG. 3, an illustrative timing diagram is depicted showingdata {tilde over (d)}(τ) and clock {tilde over (c)}(τ) signals over timefor an open clock state. In region 202, {tilde over (d)}(τ) varies(e.g., during calculations or other operations), then at τ=0 a logical“1” is to be written to the latch (106). During this period {tilde over(c)}(τ)remains high for a period of time. {tilde over (d)}(τ)and {tildeover (c)}(τ)remain high to enable the “1” to be stored or latched in thememory element (latch 106) during period τ₀. When {tilde over (c)}(τ)transitions low at τ₀ after a period of 1/Δ, the latch enters its holdstate to maintain the set value of the data. The clock {tilde over(c)}(τ) transitions between low and high or open clock and closed clockstates. The open state is given by τ≦τ₀ and the closed state is given byτ≧τ₀+1/Δ.

FIGS. 4 and 5, respectively show equivalent circuits during the openstate (FIG. 4) when data is latched and the closed state where data ismaintained in the latch.

From the latch circuit in FIG. 2, Kirchoff's laws are applied to thecircuit to yield:

$\begin{matrix}{\mspace{85mu} {{{f( v_{1} )} - v_{2}} = 0}} & (1) \\{\mspace{85mu} {{{Cv}_{3}^{\prime} - {( {1/R} )v_{2}} + {( {1/R} )v_{3}}} = 0}} & (2) \\{\mspace{85mu} {{{f( v_{3} )} - v_{4}} = 0}} & (3) \\{{{Cv}_{1}^{\prime} + {( {\frac{{Rg}( {\overset{\_}{c}(\tau)} )}{1 + {{Rg}( {\overset{\_}{c}(\tau)} )}} + {g( {c(\tau)} )}} )v_{1}} - {\frac{g( {\overset{\_}{c}(\tau)} )}{1 + {{Rg}( {\overset{\_}{c}(\tau)} )}}v_{4}}} = {{g( {c(\tau)} )}{d(\tau)}}} & (4)\end{matrix}$

the following are denoted:

${g(\tau)} = {g( {{c(\tau)};{{\overset{\_}{g}(\tau)} = {\overset{\_}{g}( {\overset{\_}{c}(\tau)} )}};{r = \frac{1}{R}};} }$

and we eliminate v₂ and v₄ to get:

$\begin{matrix}{{Cv}_{1}^{\prime} = ( {\frac{r{\overset{\_}{g}(\tau)}}{r + {\overset{\_}{g}(\tau)}} + {{g(\tau)}v_{1}} + {\frac{r{\overset{\_}{g}(\tau)}}{r + {\overset{\_}{g}(\tau)}}{f( v_{3} )}} + {{g^{\prime}(\tau)}{d(\tau)}}} } & (5) \\{{Cv}_{3}^{\prime} = {{- {rv}_{3}} + {{rf}( v_{1} )}}} & (6)\end{matrix}$

Variables are redefined as follows:

u=ν₁; v=ν₃; Ct=τ; δ=CΔ and the following functions are introduced:

${{p(t)} = \frac{r{\overset{\_}{g}( {\tau (t)} )}}{1 + {r{\overset{\_}{g}( {\tau (t)} )}}}};{{q(t)} = {g( {\tau (t)} )}};{{d(t)} = {\overset{\sim}{d}( {\tau (t)} )}}$

Making the appropriate substitutions of the introduced functions p andq, the derivatives of du/dt and dv/dt ({dot over (u)} and {dot over(v)}, respectively) are as follows:

{dot over (u)}=−(p(t)+q(t))u+p(t)f(v)+q(t)d(t)   (7)

{dot over (v)}=−rv+rf(u)   (8)

This system of ordinary differential equations cannot be solved inclosed form, but can be solved using the qualitative theory of ordinarydifferential equations.

Using known conditions, the differential equations can be solved. Forexample, as shown when the clock is closed (c(t)=0), equations 7 and 8can be plotted (u versus v as depicted in plot 223 for the circuitdiagram 222 in FIG. 6.

Referring to FIG. 6, the dynamic determination of the circuit responseduring the closed state is shown in plot 223 for equivalent circuit forthe closed state shown in FIG. 5. Regions A_((0,1)) and A_((1,0)) depicttheoretical states which can be occupied during the hold period. Σ₀ isthe safety zone for state 0 and Σ₁ is the safety zone for state “1”.Region Ω shows an area of potential metastability around inflexion point(v,v) where ν is the ideal state switching boundary. Metastability is astate where the time to reach one of the two stable states cannot bebounded, e.g., the settling time may be too long.

When clock is open (c(t)=1) and equations 7 and 8 become:

{dot over (u)}=−u+d(t)

{dot over (v)}=−rv+rf(u)

This system can be solved explicitly.

Applying a value of 1 to the latch (d(t)=1) yields:

{dot over (u)}=−u+1

{dot over (v)}=−rv+rf(u)

It may also be assumed that the start time is t=0. So, for initialconditions (u,v)=(u₀, v₀):

u(t) = (u₀ − 1)^(−t) + 1, v(t) = ^(−rt)(v₀ + ∫₀^(rt)e^(s)f(u(Rs)s).

u(t) is a monotonous function of u₀, so we get:

u(t)≧1−e ^(−t).

Referring to FIG. 7, the time needed to latch data, τ₀ (see FIG. 2),needs to be achieved. The time T_(u) needed for u(t) to reach Σ₁satisfies:

$\begin{matrix}{T_{u} \leq {\ln \frac{1}{ɛ}}} & (9)\end{matrix}$

where ε is a parameter used to define the safety regions for the openstate or clock analysis.

However, the amount of time needed to latch, e.g., a “1” needs to beT_(u) plus T_(v) since τ₀=T_(u)+T_(v), where τ₀ is equal to the set-uptime for the latch. While the value of u needs to reach Σ₁, the value ofv needs to reach ν as shown in FIG. 7. Therefore, for u>1−ε to bepreserved when the latch is closing, v<f⁻¹(1−ε). The time T_(v) can becalculated by:

$\begin{matrix}{{f^{- 1}( {1 - ɛ} )} = {{^{- {rT}_{v}}( {{v( T_{u} )} + {\int_{0}^{{rT}_{v}}{^{s}{f( {1 - {ɛ\; ^{- {Rs}}}} )}{s}}}} )}.}} & (10)\end{matrix}$

S is an integration parameter. The right hand side of the equality is anincreasing function of v(T_(u)), the function f is decreasing, so

$\begin{matrix}{ {{f^{- 1}( {1 - ɛ} )} \leq {^{- {rT}_{v}} + {\int_{0}^{{rT}_{v}}1} + {^{s}{f( {1 - ɛ} )}{s}}}} ).} & (11)\end{matrix}$

This reduces to:

$\begin{matrix}{T_{v} \leq {R\; {{\ln ( \frac{1 - {f( {1 - ɛ} )}}{{f^{- 1}( {1 - ɛ} )} - {f( {1 - ɛ} )}} )}.}}} & (12)\end{matrix}$

Equation 12 may be approximated by T_(v)≈R(1n(1/ν)). Therefore, the timeneeded to latch data into the latch can be determined. FIG. 7illustratively shows a set-up time (T_(S)) and a hold time (T_(H)) forthe latch, with the difference between these times being /δ.

Referring again to FIG. 8, an estimate of the characteristics of thelatch 104 is illustratively shown. Paths 230 and 232 show thetime-dependent change going between states.

FIG. 8 shows safety regions 120 and 122 labeled with B^(L) _(ε) andB^(R) _(ε) respectively. The safety regions are determined in accordancewith the following. If a parameter ε<ν and d(t)<ε then the set B^(L)_(ε) is an invariant set of the system provided by equations 7 and 8. Ifd(t)>1−ε, then the set B^(R) _(ε) is an invariant set of equations 7 and8. When q=0 then both sets B^(L) _(ε) and B^(R) _(ε) are invariant.

It can be seen from FIG. 8 that the bounding values of B^(L) _(ε)include ε and f⁻¹(ε) and the bounding values for B^(R) _(ε) include 1−εand f⁻¹(1−ε). FIG. 8 provides the characteristic curves against whichset and hold times for the latch can easily be computed. The set-up timeτ_(S) and hold time τ_(H) satisfy the following equations:

$\begin{matrix}{\tau_{S} \leq {{C\; \ln \frac{1}{ɛ}} + {R\; C\; {\ln ( \frac{1 - {f( {1 - ɛ} )}}{{f^{- 1}( {1 - ɛ} )} - {f( {1 - ɛ} )}} )}}}} & (13) \\{\tau_{H} = {{\tau_{S} + \frac{1}{\Delta}} \approx {{C\; \ln \frac{1}{ɛ}} + {{RC}\; \ln \frac{1}{v}} + {\frac{1}{\Delta}.}}}} & (14)\end{matrix}$

By determining the characteristic curves as provided above, the speedand accuracy of determining characteristics of circuits, e.g., memorycircuits, such as latches in significantly increased. The set and holdtimes illustratively determined above is easily performed by calculationinstead of a time consuming simulation which requires computerprocessing time and overhead.

Other advantages are provided by present invention. For example,balancing or tradeoff studies between parameters or characteristics mayeasily be performed. In one example, a tradeoff study can be performedbetween data bus and memory accessibility. Data from a data bus goingto/from a latch may be accessible earlier at the cost of wait time toretrieve the latched data. The balance can be struck by increasing thesize of the safety zone greater than B^(R) _(ε) in the design.

Having described preferred embodiments of a system and method for memoryelement characterization (which are intended to be illustrative and notlimiting), it is noted that modifications and variations can be made bypersons skilled in the art in light of the above teachings. It istherefore to be understood that changes may be made in the particularembodiments disclosed which are within the scope and spirit of theinvention as outlined by the appended claims. Having thus describedaspects of the invention, with the details and particularity required bythe patent laws, what is claimed and desired protected by Letters Patentis set forth in the appended claims.

1. A latch design system, comprising: a modeling module configured tomodel a latch using a simulation method; a simulation module configuredto determine component response characteristics for components of thelatch and compute safety regions in a state space of the latch, thesafety regions indicating stable states for the latch; and a transientanalysis module configured to determine transient responses for thelatch in an open state to geometrically determine a path and time neededto reach one of the safety regions, the path and the time being used todetermine a clock waveform for placing a corresponding state in the oneof the safety regions.
 2. The system as recited in claim 1, wherein thetransient analysis module determines set and hold times for the latchbased upon a clock waveform by employing the bounds determined for thesafety region.
 3. The system as recited in claim 1, wherein thesimulation method includes equations.
 4. The system as recited in claim1, wherein modeling the memory element using a simulation methodincludes modeling the memory element using simulation software.
 5. Thesystem as recited in claim 1, wherein the path and the time needed toreach one of the safety regions is determined based on a geometriclayout of the state space.
 6. The system as recited in claim 1, whereinthe safety regions are based on simulation experiments performed on thelatch.
 7. A design structure embodied in a machine readable medium fordesigning, manufacturing, or testing an integrated circuit, the designstructure comprising: a modeling module configured to model a latchusing a simulation method; a simulation module configured to determinecomponent response characteristics for components of the latch andcompute safety regions in a state space of the latch, the safety regionsindicating stable states for the latch; and a transient analysis moduleconfigured to determine transient responses for the latch in an openstate to geometrically determine a path and time needed to reach one ofthe safety regions, the path and the time being used to determine aclock waveform for placing a corresponding state in the one of thesafety regions.
 8. The design structure as recited in claim 7, whereinthe transient analysis module determines set and hold times for thelatch based upon a clock waveform by employing the bounds determined forthe safety region.
 9. The design structure as recited in claim 7,wherein the simulation method includes equations.
 10. The designstructure as recited in claim 7, wherein modeling the memory elementusing a simulation method includes modeling the memory element usingsimulation software.
 11. The design structure as recited in claim 7,wherein the path and the time needed to reach one of the safety regionsis determined based on a geometric layout of the state space.
 12. Thedesign structure as recited in claim 7, wherein the safety regions arebased on simulation experiments performed on the latch.